Circuit for controlling a power MOS transistor and detecting a load in series with the transistor
US6696871B2 · kind B2 · utility
4Cited by
9References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2002 |
| Grant date | Feb 24, 2004 |
| Priority date | — |
| Expiry date | Jun 6, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The detection of the presence of a load associated with a power MOS transistor integrated with its control circuit using a filtering time delay in generating a detection signal with respect to the occurrence of a turn-off control order of the power transistor, and where the filtering time delay is controlled with the power transistor switching time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.