Signal transfer system, signal transfer apparatus, display panel drive apparatus, and display apparatus
US6697038B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 1, 2001 |
| Grant date | Feb 24, 2004 |
| Priority date | — |
| Expiry date | May 21, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G3/3688
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A plurality of signal input-output sections are connected with each other in a cascade manner. In each signal input-output section, an input latch circuit divides a data signal into 2 channels in accordance with the first clock signal, and an output latch circuit returns the data signal that has been divided into 2 channels to 1 channel in accordance with the second clock signal so as to be outputted to the signal input-output section of the next stage. The inputted first basic clock is outputted to the signal input-output section of the next stage as the second basic clock, and the inputted second basic clock is outputted to the signal input-output section of the next stage as the first basic clock. This allows to ensure the data sampling margin even when the data signal should be transferred at a faster speed, and also allows to suppress the problem of the EMI.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.