Content addressable memory (CAM) having a match line circuit with selectively adjustable pull-up impedances
US6697277B2 · kind B2 · utility
15Cited by
10References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 23, 2003 |
| Grant date | Feb 24, 2004 |
| Priority date | — |
| Expiry date | Apr 23, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A match line circuit in a content addressable memory (CAM) has a match line coupled to a first pull-up device and a first pull-down device at a match node. The first pull-up device has selectively adjustable pull-up impedances associated with it. The match line circuit also includes a second pull-up device coupled to a second pull-down device at a float node, and an enabling signal for activating the match line circuit during a memory comparison operation. The enabling signal precharges the match node to a logic low level and the float node to a logic high level in between memory comparison operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.