Distributed switch memory architecture
US6697362B1 · kind B1 · utility
20Cited by
7References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 6, 1998 |
| Grant date | Feb 24, 2004 |
| Priority date | — |
| Expiry date | Nov 6, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/351
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A distributed memory switch system for transmitting packets from source ports to destination ports, comprising: a plurality of ports including a source port and a destination port wherein a packet is transmitted from the source port to the destination port; a memory pool; and an interconnection stage coupled between the plurality of ports and the memory pool such that the interconnection stage permits a packet to be transmitted from the source port to the destination port via the memory pool.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.