Optimized method and apparatus for parallel leading zero/one detection
US6697828B1 · kind B1 · utility
4Cited by
5References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 1, 2000 |
| Grant date | Feb 24, 2004 |
| Priority date | — |
| Expiry date | Feb 1, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/74
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for detecting leading zeros in a number represented by a plurality of four-bit nibbles, each nibble having an associated order of significance, said method comprising is disclosed. The leading zero detector calculates a leading zero count for each nibble in parallel, associates with each nibble count calculation a bit value inversely corresponding to the nibble's order of significance, and selects the nibble count calculation which corresponds to the highest order nibble without all zero values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.