Memory controller and method control method, and rendering device and printing device using the same
US6697882B1 · kind B1 · utility
9Cited by
4References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 21, 2000 |
| Grant date | Feb 24, 2004 |
| Priority date | — |
| Expiry date | Feb 18, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A rendering processor has source, pattern, destination prefetch/write units and DMA controllers. Each DMA controller enqueues a transaction such as a memory read/write in a transaction queue. A memory controller processes transactions in the queue in the FIFO order. A prefetch unit determines whether or not data is prefetched to a line end, and if the determination is affirmative, postpones a prefetch until completion of the write-back of the prefetched data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.