Data communication interface between host and slave processors
US6697897B1 · kind B1 · utility
54Cited by
5References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 27, 2000 |
| Grant date | Feb 24, 2004 |
| Priority date | — |
| Expiry date | Dec 31, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L5/1423
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A data communication interface for transferring at least one data bit to a host processor. The interface includes a one-wire data line, and a slave processor connected to the data line and including a pull-down circuit for varying voltage on the data line. The slave processor is passive and incapable of sampling data from the data line. The slave processor is programmed to vary voltage on the data line when the data line is energized, to signal at least one data bit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.