Signal processor providing an increased memory access rate
US6697921B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 7, 2001 |
| Grant date | Feb 24, 2004 |
| Priority date | — |
| Expiry date | Aug 7, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4018
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The bus width of the data bus among blocks for transferring data among respective blocks such as the memory control block, the error correction block, and the host I/F block is 32-bit width, and the bus width of the memory data bus for transferring data between the buffer memory and the memory control block is 64-bit width, whereby an access to the buffer memory is performed by the unit of 64 bits, while respective block processings are performed by the unit of 32 bits out of the 64 bits. Therefore, 32-bit data transferred through the data bus among blocks are always valid data, whereby the access rate from respective blocks in the system to the buffer memory can be increased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.