Buffer management method and a controller thereof
US6697923B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2001 |
| Grant date | Feb 24, 2004 |
| Priority date | — |
| Expiry date | May 9, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for buffer management and a controller of the same are disclosed. In the buffer management method, a first control mode is performed, and a plurality of bits are used to control a bit mask region of a memory. A second control mode is performed, and a plurality of unused addresses in a link region of the memory is cached. A third control mode is performed, to control a plurality of second unused addresses in the link region by a linked list. The controller comprises a plurality of bits for controlling a bit mask region; a plurality of address cache units for caching a plurality of first unused address of a linked list in a link region; and a pointer for always pointing to a head of the linked list in the link region, wherein the linked list links a plurality of second unused addresses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.