Interleaver design for parsed parallel concatenated codes
US6697990B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2000 |
| Grant date | Feb 24, 2004 |
| Priority date | — |
| Expiry date | Apr 3, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6362
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for interleaving an input data stream for parsed parallel concatenated code encoding, the method comprising the steps of: parsing the input data stream into a plurality of parsed data substreams; and forming sets of shared information bits, wherein each of the sets of shared information bits comprises information bits in common with respective pairs of the plurality of parsed data substreams. In a variation, a further step comprises constructing constituent permutations of one or more of the sets of shared information bits. In yet a further variation, a further step comprises interlacing respective pairs of the sets of shared information bits to form respective interleaved data substreams.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.