Stacked microelectronic assembly and method therefor
US6699730B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 2, 2001 |
| Grant date | Mar 2, 2004 |
| Priority date | — |
| Expiry date | Jun 7, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of making a stacked microelectronic assembly includes providing a flexible substrate having a plurality of attachment sites, test contacts and conductive terminals, and including a wiring layer with leads extending to the attachment sites. The method includes assembling a plurality of microelectronic elements to the attachment sites and electrically interconnecting the microelectronic elements and the leads. The flexible substrate is then folded so as to stack at least some of the microelectronic elements in substantially vertical alignment with one another to provide a stacked assembly with the conductive terminals exposed at the bottom end of the stack and the test contacts exposed at the top end of the stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.