Surface mounting substrate having bonding pads in staggered arrangement
US6700208B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 18, 2000 |
| Grant date | Mar 2, 2004 |
| Priority date | — |
| Expiry date | Nov 6, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A surface mounting substrate is configured to surface mount a semiconductor element thereon, the semiconductor element having a plurality of protruding electrodes arranged in a staggered arrangement of two rows. A plurality of bonding pads formed on a substrate are arranged in a staggered arrangement corresponding to the staggered arrangement of the protruding electrodes of the semiconductor element. Each of the bonding pads includes a pad portion having a substantially uniform width and an end portion extending from the pad portion toward the other row of the bonding pads. The end portion of each of the bonding pads lacks a portion extending beyond a boundary between the end portion and the pad portion of the bonding pads arranged in the other row. Accordingly, a reliable mounting can be achieved even if the protruding electrodes are offset from bonding pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.