Cam circuit with error correction
US6700827B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 23, 2002 |
| Grant date | Mar 2, 2004 |
| Priority date | — |
| Expiry date | Aug 23, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/046
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A CAM circuit including a RAM array, a CAM array, a control/interface circuit, and an error detection and correction (EDC) circuit. The control/interface circuit systematically writes data from the RAM array to the CAM array, thereby preventing soft errors by continually refreshing data stored in the CAM array. The RAM array also stores check bits for each data word that can be generated by the EDC circuit when the data words are initially written to the CAM circuit. During the refresh operation, data words and associated check bits are read from the RAM array and transmitted to the EDC circuit. The EDC circuit analyzes each data word and associated check bits to detect errors, and corrects the data word, if necessary, before sending the data word to the CAM array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.