Digital receive phase lock loop with cumulative phase error correction and dynamically programmable correction rate
US6701140B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 14, 2000 |
| Grant date | Mar 2, 2004 |
| Priority date | — |
| Expiry date | Jun 20, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0331
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A digital phase lock loop (PLL) for maintaining synchronization with the phase of a received data signal including a preamble and an information-containing data frame, by incrementing a state machine through an internal cyclic count, each cycle thereof including a center count tending to coincide with center regions of the successive pulses and an edge count tending to coincide with edges of the successive pulses. The PLL selects a current sample of the signal whenever the internal count reaches the predetermined center count value. The state machine internal count is updated in accordance with a cumulative phase error obtained by summing the phase errors detected over successive edges between each edge and the corresponding center count. The interval over which the cumulative phase error is computed depends upon the number of received edges during the preamble and depends upon elapsed time during the data frame.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.