FIFO buffer that can read and/or write multiple and/or selectable number of data words per bus cycle
US6701390B2 · kind B2 · utility
12Cited by
13References
12Claims
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Key dates
| Filing date | Jun 6, 2001 |
| Grant date | Mar 2, 2004 |
| Priority date | — |
| Expiry date | Apr 30, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A first in, first out (FIFO) circular buffer enables high speed streaming data transfer between integrated circuit devices by performing more than one data element transfer unidirectionally by having a plurality of ports to address a memory array. In addition, the multiple transfers are performed during one bus cycle and the number of transfers may be selectable. FIFO control circuitry limits the number of data elements transferred in response to the state of the memory array including almost empty or almost full.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.