Pre-arbitration request limiter for an integrated multi-master bus system
US6701397B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2000 |
| Grant date | Mar 2, 2004 |
| Priority date | — |
| Expiry date | Mar 21, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/3625
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method and structure for dynamically blocking access of a request signal R to a shared bus such that R originates from a non real-time master and requests access to an address range of an address space. The shared bus manages requests for access to the address space. The non real-time master and a real-time master compete for access to the address space by presenting address access requests to the shared bus. The dynamic blocking of access by R to the shared bus is accomplished by use of a request limiter, which is a device that is coupled to a real-time clock and uses an algorithm to determine when to enable and disable access of R to the shared bus. The algorithm uses a windowing scheme that permits access of R to the shared bus every Nth clock cycle, wherein the value of the integer N may be supplied to the request limiter by the real-time master. An example of the algorithm includes blocking access of R to the shared bus whenever all of the following conditions occur: the real-time master has a non-empty internal queue, the real master and the non real master are both requesting access to a same address range of the address space, and the real-time clock is not at the Nth clo…
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