Global bus synchronous transaction acknowledge with nonresponse detection
US6701398B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 6, 2000 |
| Grant date | Mar 2, 2004 |
| Priority date | — |
| Expiry date | Apr 6, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4068
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated multi-processor system with clusters of processors on a high speed split transaction bus uses a transaction acknowledge (TACK), by a target device in response to receiving a request from a master device on the bus. The master and target devices connect to the bus via a global bus interface with FIFO registers acting as buffers, and the target interface includes a TACK generator that flips the state of the global bus' TACK line upon determining that a broadcast request is addressed to its target device. A bus idle default device (BIDD) generates a TACK signal when no device is on the bus, and also detects the absence of any TACK response by monitoring the state of the TACK line, thereby indicating that a master device bus attempted to address a nonexistent target a device. The BIDD then generates a dummy response for the requesting master device with data flags set to invalid data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.