Priority mechanism for scheduling isochronous and asynchronous transactions on a shared bus
US6701399B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 29, 2000 |
| Grant date | Mar 2, 2004 |
| Priority date | — |
| Expiry date | Feb 29, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/3625
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A plurality of asynchronous and isochronous transactions on a shared bus are scheduled such that asynchronous latency is minimized while providing a maximum latency for isochronous transactions. This is accomplished by splitting an allocated shared bus time into frames of equal length. When a bus request is received the technique determines whether the bus request in a current frame is for an asynchronous transaction or an isochronous transaction. If an asynchronous transaction bus request exists it is processed, otherwise an isochronous transaction bus request is processed. Bus requests for an isochronous transaction are queued if received while an asynchronous transaction is currently being processed. Asynchronous transactions are given priority until a current frame time has ended. In one embodiment, at the start of a new frame (which becomes the current frame) any queued isochronous transactions are processed before asynchronous transactions of the current frame are given priority. In another embodiment, queued isochronous transactions are only processed at the start of a new frame if they are from two frames prior to the new frame.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.