Memory control system with incrementer for generating speculative addresses
US6701422B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 29, 2001 |
| Grant date | Mar 2, 2004 |
| Priority date | — |
| Expiry date | Apr 9, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0215
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller includes an incrementer for predicting a next address to be asserted by a processor. The incrementer, structurally a counter, is configurable to wrap at a wrap boundary and to indicate when a predicted address crosses a page boundary if the memory is in page mode. This incrementer provides accurate predictions even where successor addresses are on different pages or, in the case of address loops, even in some cases in which the successor address is not consecutive. Thus, the number of accurate address predictions is increased, enhancing overall performance. The invention has particular applicability to signal processing applications with instructions loops that cross one or more page boundaries.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.