Register file with delayed parity check
US6701484B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2000 |
| Grant date | Mar 2, 2004 |
| Priority date | — |
| Expiry date | Sep 11, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/229
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A register for a computer processor removes the parity check from the critical path of CPU operation, and delays the parity check to the next immediate clock cycle. The register has a memory array, and read and write decoders for accessing the memory array using select lines. The select lines are also connected to read and write address latches which are used to index a parity bit array. When a value is written to, or read from, the memory array, its corresponding parity bit is calculated and either stored in the parity bit array (for a write operation), or compared to an existing parity bit array entry (for a read operation). The parity check is performed on a copy of the value contained in a read data latch or a write data latch. Each data latch has an input connected to a respective read or write port of the memory array. The latches delay the parity check by only one cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.