Method of using testbench tests to avoid task collisions in hardware description language
US6701494B2 · kind B2 · utility
30Cited by
10References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 1, 2002 |
| Grant date | Mar 2, 2004 |
| Priority date | — |
| Expiry date | May 1, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and system for performing simultaneous tests and avoiding task collisions using a hardware description language includes designating a timeslot for one or more of the simultaneous tests, associating the designated timeslot with one or more of the tasks to be performed in a test, determining if the designated timeslot is available before executing the tasks associated with timeslots and executing the tasks when the designated timeslots become available.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.