Black box timing model for latch-based systems
US6701498B2 · kind B2 · utility
8Cited by
18References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 8, 2001 |
| Grant date | Mar 2, 2004 |
| Priority date | — |
| Expiry date | Nov 9, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of creating a black box timing model for a digital circuit. The digital circuit is characterized by a block model having at least one input and at least one output. The method determines a delay statement for the output of the block model. The method also determines an input set-up constraint for the input of the block model. The input set-up constraint is based upon the delay statement. The model is then used with a static timing analyzer to accurately model a flow-through circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.