Method for fabricating LC device using latent masking and delayed LOCOS techniques
US6702950B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Nov 2, 2001 |
| Grant date | Mar 9, 2004 |
| Priority date | — |
| Expiry date | Jun 6, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/942
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Three fundamental and three derived aspects of the present invention are disclosed. The three fundamental aspects each disclose a process sequence that may be integrated in a full process. The first aspect, designated as “latent masking”, defines a mask in a persistent material like silicon oxide that is held abeyant after definition while intervening processing operations are performed. The latent oxide pattern is then used to mask an etch. The second aspect, designated as “simultaneous multi-level etching (SMILE)”, provides a process sequence wherein a first pattern may be given an advanced start relative to a second pattern in etching into an underlying material, such that the first pattern may be etched deeper, shallower, or to the same depth as the second pattern. The third aspect, designated as “delayed LOCOS”, provides a means of defining a contact hole pattern at one stage of a process, then using the defined pattern at a later stage to open the contact holes. The fourth aspect provides a process sequence that incorporates all three fundamental aspects to fabricate an integrated liquid chromatography (LC)/electrospray ionization (ESI) dev…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.