Method of reducing NMOS device current degradation via formation of an HTO layer as an underlying component of a nitride-oxide sidewall spacer
US6703282B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 2002 |
| Grant date | Mar 9, 2004 |
| Priority date | — |
| Expiry date | Jul 2, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/0217
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming an NMOS device with reduced device degradation, generated during a constant current stress, has been developed. The reduced device degradation is attributed to the use of a high temperature oxide (HTO), layer, used as an underlying component of composite insulator spacers, formed on the sides of the NMOS gate structures. After definition of an insulator capped polycide gate structure a thin, (140 to 160 Angstrom), HTO layer is deposited at a temperature between about 700 to 800° C., followed by the deposition of a silicon nitride layer. Definition of the composite insulator layer, comprised with the underlying, HTO, results in NMOS devices with reduced drain current and reduced transconductance values, when compared to counterparts fabricated with composite insulator spacers formed without the thin, HTO layer featured in this invention.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.