Power FET device

US6703664B1 · kind B1 · utility

Assignee

• Zetex PLC · GB

Inventor

• Paul Anthony Jerred · Manchester, GB

Key dates

• Filing date: Mar 31, 2000
• Grant date: Mar 9, 2004
• Expiry date: Mar 31, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/519

Abstract

A power FET device includes a semiconductor wafer substrate having first and second surfaces, a gate electrode extending over the first surface of the substrate but insulated therefrom, and a drain electrode extending over the second surface of the substrate. The gate electrode defines a regular array of apertures. An FET body region of a first conductivity type is formed in the first surface of the substrate beneath each gate electrode aperture, each body region extending laterally from edges of the gate electrode defining the aperture. An FET source region of a second conductivity type is formed within the body region beneath each gate electrode aperture, each FET source region extending from the edges of the gate electrode a second distance less than the first distance. An FET channel region extends around the periphery of each source region. Pairs of adjacent gate electrode apertures define there between a strip of gate electrode the width of which varies along the length of the strip. As a result body dopant introduced through adjacent gate electrode apertures merges to form a single body structure extending continuously beneath the apertures.