Transistor
US6703665B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 17, 2000 |
| Grant date | Mar 9, 2004 |
| Priority date | — |
| Expiry date | Aug 17, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/517
Abstract
A withstand voltage region of a second conductivity type is formed in a drain layer of a first conductivity type in a semiconductor substrate, and a conductive region of the first conductivity type is partly formed in the withstand voltage region by being diffused from the surface of the withstand voltage region. The conductive region has a bottom held in contact with the drain layer. A base region and a source region are formed in the surface of semiconductor substrate, with a region between the source region and the conductive region serving as a channel region, thus producing a transistor. When a voltage is applied to a gate electrode film on the channel region to form an inverted layer, the source region and the drain layer are connected to each other by the inverted layer and the conductive region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.