Architecture and interconnect scheme for programmable logic circuits
US6703861B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 11, 2002 |
| Grant date | Mar 9, 2004 |
| Priority date | — |
| Expiry date | Oct 22, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17796
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An architecture and distributed hierarchical interconnect scheme for field programmable gate arrays (FPGAs). The FPGA is comprised of a number of cells which perform logical functions on input signals. Programmable intraconnections provide connectability between each output of a cell belonging to a logical cluster to at least one input of each of the other cells belonging to that logical cluster. A set of programmable block connectors are used to provide connectability between logical clusters of cells and accessibility to the hierarchical routing network. An uniformly distributed first layer of routing network lines is used to provide connections amongst sets of block connectors. An uniformly distributed second layer of routing network lines is implemented to provide connectability between different first layers of routing network lines. Switching networks are used to provide connectability between the block connectors and routing network lines corresponding to the first layer. Other switching networks provide connectability between the routing network lines corresponding to the first layer to routing network lines corresponding to the second layer. Additional uniformly distribute…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.