Dual match-line, twin-cell, binary-ternary CAM
US6704216B1 · kind B1 · utility
22Cited by
16References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2002 |
| Grant date | Mar 9, 2004 |
| Priority date | — |
| Expiry date | Aug 16, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A content addressable memory (CAM)(10, 102) and method having a data-in sub-circuit (44), memory cells (16, 18), a match-high line (36), a match-low line (38), and pre-charge devices (40, 42). Input lines (30, 32, 48, 50) from the data-in sub-circuit (44) are not necessarily discharged to ground in every cycle of a clock signal (62) used by the memory cells (16, 18). Further, the pre-charge devices (40, 42) may be operated at one half of the rate of the clock signal (62). Yet further, the CAM (10, 102) may be selectively configured to operate in either binary or ternary mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.