Floating gate programmable cell array for standard CMOS
US6704221B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 5, 2001 |
| Grant date | Mar 9, 2004 |
| Priority date | — |
| Expiry date | Jun 2, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/045
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A new floating gate programmable device cell is achieved. The device comprises, first, a negative injection transistor having drain, source, bulk, and gate. The source and bulk are coupled to ground. The drain forms an output of the cell. A positive injection transistor has drain, source, bulk, and gate. The drain, source, and bulk are coupled to a programming voltage. The gate is coupled to the negative injection transistor gate to form a floating gate node. Finally, a capacitor has a first terminal coupled to the floating gate node and a second terminal coupled to a control voltage. The states of the programming voltage and the control voltage determine negative charge injection onto the floating gate node and positive charge injection onto the floating gate node. A voltage on the floating gate node comprises a nonvolatile memory state that is detectable by the impedance of the output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.