Method and apparatus for verification of a gate oxide fuse element
US6704236B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 3, 2002 |
| Grant date | Mar 9, 2004 |
| Priority date | — |
| Expiry date | Jan 20, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/38
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and circuit for verifying the state of a gated fuse element used with a one-time programmable CMOS memory device. A first expected state is set and a state of a first gate-ox fuse is sensed. The state of the first gate-ox fuse is compared to the first expected state to determine if they are equal, and a first signal is generated. A second expected state is set and a state of a second gate-ox fuse is sensed. The state of the second gate-ox fuse is compared to the second expected state to determine if they are equal, and a second signal is generated. A valid output is generated if both the first and second signals are in a correct state, both signals are high for example.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.