Frequency acquisition rate control in phase lock loop circuits
US6704381B1 · kind B1 · utility
62Cited by
7References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 17, 1999 |
| Grant date | Mar 9, 2004 |
| Priority date | — |
| Expiry date | Sep 17, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate (i) a first reference signal in response to a pump-up signal and (ii) a second reference signal in response to a pump-down signal. The second circuit may be configured to generate (a) a first control signal in response to (i) the pump-up signal and (ii) the second reference signal and (b) a second control signal in response to (i) the pump-down signal and (ii) the first reference signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.