Multi-chip semiconductor module and manufacturing process thereof
US6704609B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 18, 2000 |
| Grant date | Mar 9, 2004 |
| Priority date | — |
| Expiry date | Jul 24, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15787
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multi-chip semiconductor module includes first and second substrates. The first substrate has opposite first and second surfaces, a plurality of first conductive vias that extend through the first and second surfaces, and a first circuit layout patterned on the second surface and connected electrically to the first conductive vias. The second substrate has opposite first and second surfaces, a plurality of second conductive vias that extend through the first and second surfaces of the second substrate, a second circuit layout patterned on the second surface of the second substrate and connected electrically to the second conductive vias, and a chip-receiving opening formed therein. The first surface of the second substrate is bonded on the second surface of the first substrate such that the second circuit layout is connected electrically to the first circuit layout through the first and second conductive vias. A first semiconductor chip is disposed in the chip-receiving openings, and has a first contact pad surface mounted on the second surface of the first substrate and formed with a plurality of first contact pads that are connected to the first circuit layout. A second semicon…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.