Computer architecture and system for efficient management of bi-directional bus
US6704817B1 · kind B1 · utility
46Cited by
22References
32Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2000 |
| Grant date | Mar 9, 2004 |
| Priority date | — |
| Expiry date | Oct 4, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4059
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An efficient system and method for managing reads and writes on a bi-directional bus to optimize bus performance while avoiding bus contention and avoiding read/write starvation. In particular by intelligently managing reads and writes on a bi-directional bus, bus latency can be reduced while still ensuring no bus contention or read/write starvation. This is accomplished by utilizing bus streaming control logic, separate queues for reads and writes, and a simple 2 to 1 mux.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.