Arbitration protocol for a shared data cache
US6704822B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 1999 |
| Grant date | Mar 9, 2004 |
| Priority date | — |
| Expiry date | Oct 1, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1605
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and computer system for resolving simultaneous requests from multiple processing units to load from or store to the same shared resource. When the colliding requests come from two different processing units, the first processing unit is allowed access to the structure in a predetermined number of sequential collisions and the second device is allowed access to the structure in a following number of sequential collisions. The shared resource can be a fill buffer, where a collision involves attempts to simultaneously store in the fill buffer. The shared resource can be a shared write back buffer, where a collision involves attempts to simultaneously store in the shared write back buffer. The shared resource can be a data cache unit, where a collision involves attempts to simultaneously load from a same data space in the data cache unit. A collision can also involve an attempt to load and store from a same resource and in such case the device that attempts to load is favored over the device that attempts to store.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.