Mechanism for executing computer instructions in parallel
US6704861B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 1996 |
| Grant date | Mar 9, 2004 |
| Priority date | — |
| Expiry date | Oct 26, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3865
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A mechanism for executing computer instructions in parallel includes a compiler for generating and grouping instructions into a plurality of sets of instructions to be executed in parallel, each set having a unique identification. A computer system having a real state and a speculative state executes the sets in parallel, the computer system executing a particular set of instructions in the speculative state if the instructions of the particular set have dependencies which can not be resolved until the instructions are actually executed. The computer system generates speculative data while executing instructions in the speculative state. Logic circuits are provided to detect any exception conditions which occur while executing the particular set in the speculative state. If the particular set is subject to an exception condition, the instructions of the set are re-executed to resolve the exception condition, and to incorporate the speculative data in the real state of the computer system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.