Reducing sleep mode subthreshold leakage in a battery powered device by making low supply voltage less than twice the threshold voltage of one device transistor
US6704880B2 · kind B2 · utility
13Cited by
6References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2001 |
| Grant date | Mar 9, 2004 |
| Priority date | — |
| Expiry date | Nov 30, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Leakage power consumption may be reduced in computers and other devices by providing a state where clocks are off and a low supply voltage is provided to the processor. This voltage may be sufficiently low to prevent adverse consequences while dramatically reducing leakage current. In addition, caches may be flushed to reduce the soft error rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.