Data bit-to-clock alignment circuit with first bit capture capability
US6704882B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 22, 2001 |
| Grant date | Mar 9, 2004 |
| Priority date | — |
| Expiry date | Jul 29, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/06
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A circuit for aligning the phase of a parallel data signal to a clock signal. The circuit includes a parallel data terminal for receiving a parallel data signal formed by multiple word bits, a clock terminal for receiving a clock signal, and a data ready terminal for receiving a data ready signal which has a logic state transition aligned with a first information bit of the parallel data signal. A plurality of data signal delay and sampling circuits connected to the clock terminal and the parallel data terminal provide time-slice bit samples of each information bit of the parallel data signal. A comparator and decision circuit coupled to the clock terminal and at least one of the data signal delay and sampling circuits compares and selects one of the plurality of time-slice bit samples which is phase aligned with the clock signal. A multiplexer circuit coupled to each data signal delay and sampling circuit and to the comparator and decision circuit outputs the selected time-slice bit sample of each word bit of the parallel data signal as the phase-aligned parallel data signal. A first-bit intialization circuit connected to the clock terminal and the data ready terminal and coupled …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.