Automated clock alignment for testing processors in a bypass mode
US6704892B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2000 |
| Grant date | Mar 9, 2004 |
| Priority date | — |
| Expiry date | Sep 12, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318594
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
In a bypass mode, a tester may bypass the core and input/output phase locked loops (PLLs) utilized by a processor to develop internal clock signals. External, tester-generated, phase shifted clock signals may be used to generate aligned high frequency signals to replace those generated by the phase locked loops. A plurality of phase shifted, tester generated clock signals may be subjected to an exclusive OR operation for generating input/output and core clock replacement signals. The clock signals received from the tester may also be aligned. Thus, a variety of skews may be compensated before entering the bypass mode. In some embodiments of the present invention, the core and I/O PLL clocks are used to establish alignment in a set-up phase and in other embodiments, the core and I/O PLL need not be utilized at all to generate appropriate internal clock signals from an external tester.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.