Method and apparatus for automatically generating a phase lock loop (PLL)
US6704908B1 · kind B1 · utility
23Cited by
7References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 6, 2000 |
| Grant date | Mar 9, 2004 |
| Priority date | — |
| Expiry date | Sep 10, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/08
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method that automatically generates a design for an analog phase lock loop (PLL) core in response to a desired clock frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.