Method and apparatus for wafer-level burn-in and testing of integrated circuits
US6707065B2 · kind B2 · utility
5Cited by
20References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2002 |
| Grant date | Mar 16, 2004 |
| Priority date | — |
| Expiry date | Sep 16, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/316
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
In one embodiment, a testing regimen is implemented to reduce test time. Specifically, a structure and method to power up and stabilize all die on the wafer prior to testing each die is implemented. More specifically, parallel powering schemes including die stabilization procedures are used to ready the wafer for testing. A wafer probe tester is indexed from one die to the next for an uninterrupted testing of all die in the wafer subsequent to all die power up and stabilization.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.