Method of deforming a pattern and semiconductor device formed by utilizing deformed pattern
US6707107B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 26, 2001 |
| Grant date | Mar 16, 2004 |
| Priority date | — |
| Expiry date | Jun 26, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of deforming a pattern comprising the steps of forming, over a substrate, a layered-structure with an upper surface including at least one selected region and at least a re-flow stopper groove, wherein the re-flow stopper groove extends outside the selected region and separate from the selected region; selectively forming at least one pattern on the selected region; and causing a re-flow of the pattern, wherein a part of an outwardly re-flowed pattern is flowed into the re-flow stopper groove, and then an outward re-flow of the pattern is restricted by the re-flow stopper groove extending outside of the pattern, thereby to form a deformed pattern with at least an outside edge part defined by an outside edge of the re-flow stopper groove.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.