Analog to digital converter with a calibration circuit for compensating for coupling capacitor errors, and a method for calibrating the analog to digital converter
US6707403B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 12, 2002 |
| Grant date | Mar 16, 2004 |
| Priority date | — |
| Expiry date | Nov 12, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/804
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An ADC (1) of balanced architecture for determining a digital word corresponding to a sampled voltage of an input signal from an input line (33) comprises a first capacitor circuit (2) comprising a most significant capacitor array (4) and a least significant capacitor array (5) which are capacitively coupled by a coupling capacitor Cc1. A second capacitor circuit (29) coupled to ground balances the first capacitor circuit (2). A differential comparator 27 compares the voltage on the first capacitor circuit (2) with that on the second capacitor circuit (29). A SAR (42) responsive to the output of the differential comparator (27) outputs switch bits to a main switch network (32) for selectively switching the capacitors of the first capacitor circuit (2) to respective high and low voltage reference lines (34) and (35) until the voltage on first and second inputs (26) and (28) of the differential comparator (27) are equal for determining the digital word corresponding to the sampled voltage on the input line (33). A first calibration circuit (49) for calibrating the coupling capacitor (Cc1) for compensating for under or over capacitance of the coupling capacitor Cc1 comprises a plurali…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.