Register without restriction of number of mounted memory devices and memory module having the same
US6707726B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jul 29, 2002 |
| Grant date | Mar 16, 2004 |
| Priority date | — |
| Expiry date | Jul 29, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/107
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
First and second pre-processing flip-flops latch a command/address signal inputted to a register by a clock having a frequency of ½ of an external clock signal and an inverse clock thereof. Thus, the command/address signal is decomprossed to a set of signals which temporarily has two times. For example, one of the set of signals has only data contents of an odd-th command/address signal, and the other has only data contents of an even-th command/address signal. Since the set of signals has twice periods of the command/address signal, first and second post-processing flip-flop can latch signals in accordance with an internal clock signal generated by a delay locked loop circuit in a state in which a set-up time and a hold time are sufficiently assured.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.