Semiconductor memory device with efficient and reliable redundancy processing
US6707730B2 · kind B2 · utility
11Cited by
1References
15Claims
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Key dates
| Filing date | Feb 6, 2002 |
| Grant date | Mar 16, 2004 |
| Priority date | — |
| Expiry date | Mar 10, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/816
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a data buffer for inputting/outputting data from/to an exterior of the device, a plurality of DRAM cell array blocks, an SRAM redundancy cell which is situated around each of the plurality of DRAM cell array blocks, a fuse circuit which stores therein an address of a defect memory cell in the DRAM cell array blocks, a comparison circuit which compares an input address with the address stored in the fuse circuit, and an I/O bus which couple the SRAM redundancy cell to the data buffer in response to an address match found by the comparison circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.