Spreadsheet driven I/O buffer synthesis process
US6708144B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 27, 1997 |
| Grant date | Mar 16, 2004 |
| Priority date | — |
| Expiry date | Dec 23, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a method and apparatus for efficiently managing the I/O design of an integrated circuit. The present invention automatically selects and interconnects a number of I/O cells selected from a design library to form an I/O interface. A user interface is provided for receiving a number of parameters provided by the circuit designer. The parameters preferably provide specific information about a circuit design. A set of circuit design assembly rules are also provided, which define the available I/O cells and the appropriate interconnections of the available I/O cells. A computer program then selects and assembles the I/O cells in accordance with the user provided parameters and the set of circuit design assembly rules.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.