Bus control apparatus
US6708236B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 27, 2000 |
| Grant date | Mar 16, 2004 |
| Priority date | — |
| Expiry date | Jan 27, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N2201/0093
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Bus control apparatus solves the problem that a high-speed bus which supports only burst transfer cannot be used when the boundary of a transfer memory address is not coincident with a unit boundary. A scanner controller and printer controller connected to a G bus capable of performing only burst transfer and a B bus capable of performing even single transfer determine from the address and data length of data to be transferred whether the data does not match the memory boundary. If the data does not match this boundary, a data portion which is not accommodated within the burst transfer unit is single-transferred using the B bus. A data portion which is accommodated within the burst transfer unit is burst-transferred using the G bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.