Semiconductor device and manufacturing method thereof
US6709902B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 4, 2002 |
| Grant date | Mar 23, 2004 |
| Priority date | — |
| Expiry date | Mar 11, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6743
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
The present invention provides a semiconductor device in which a bottom-gate TFT or an inverted stagger TFT arranged in each circuit is suitably constructed in conformity with the functionality of the respective circuits, thereby attaining an improvement in the operating efficiency and reliability of the semiconductor device. In the structure, LDD regions in a pixel TFT are arranged so as not to overlap with a channel protection insulating film and to overlap with a gate electrode by at least a portion thereof. LDD regions in an N-channel TFT of a drive circuit is arranged so as not to overlap with a channel protection insulating film and to overlap with a gate electrode by at least a portion thereof. LDD regions in a P-channel TFT of the drive circuit is arranged so as to overlap with a channel protection insulating film and to overlap with the gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.