Printed circuit board having buried intersignal capacitance and method of making
US6710255B2 · kind B2 · utility
8Cited by
16References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2001 |
| Grant date | Mar 23, 2004 |
| Priority date | — |
| Expiry date | Aug 12, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/09672
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A first signal path is connected to a first plane via a plated hole. A first metal flood is connected to the plated hole to form a first plate. A second signal path is on a second plane. A second metal flood connected to the second signal path to form a second plate above the first plate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.