Gain control circuit with well-defined gain states
US6710657B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 12, 2001 |
| Grant date | Mar 23, 2004 |
| Priority date | — |
| Expiry date | Oct 12, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45702
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A current steering-type gain control circuit provides a non-zero minimum gain in response to readily reproducible control signal conditions and without requiring sophisticated control-signal-generating circuitry. The gain control circuit is adapted from a conventional differential pair of current-steering transistors, biased by first and second control signals respectively. To provide a well-defined non-zero minimum gain, the gain control circuit includes at least one additional current steering transistor that further steers current to the output when conducting in the minimum gain state. By further including one or more additional pairs of current steering transistors, the gain control circuit also provides a plurality of well-defined states with gains between the maximum and minimum gain values of the circuit. The minimum and intermediate gain values, may be selected by varying the physical characteristics of the current steering transistors which may be BJTs or FETs. The circuit may be implemented in a single-ended or differential configuration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.