Power amplifier with improved linearity and reduced transistor stacks
US6710662B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 16, 2002 |
| Grant date | Mar 23, 2004 |
| Priority date | — |
| Expiry date | Sep 16, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/189
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A power amplifier includes drains and sources of a plurality of transistors connected to each other to produce a plurality of common drains and a plurality of common sources, wherein the common drains are connected at a common drain point and wherein the common drain point is connected via an RF choke to a power supply voltage terminal and wherein the common sources are grounded; an output terminal connected to the RF choke; a plurality of bias terminals each coupled via a resistor to the gate of one of the plurality of transistors wherein each of the gates of the plurality of transistors is also capacitively coupled to a radio frequency input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.